With complexity of sub-90nm SOCs driving the need for test to be integrated throughout the design process, both of EDA’s largest vendors today introduced major upgrades to their respective offerings.

Because electronic systems for all applications in end-user markets must provide the highest possible reliability to match customers’ quality expectations, semiconductor components undergo multiple ...

Shipping high-quality ICs requires that design-for-test (DFT) methodologies be included in a design. DFT provides external access at the device’s I/O pins to internal registers to either control or ...

Fig. 1. Standard method used for displaying fatigue test results. 1a (right) shows standard fatigue testing terminology, and 1b. (left) depicts an S-N diagram. Photo Credit: Dan Adams Fatigue testing ...